This invention relates to circuitry for converting digital signals to analog signals, and more particularly to circuitry for performing arithmetic addition, subtraction, multiplication and/or division concurrently with a change in representation of numerical values from a plurality of binary coded digital signals to a pair of binary signals representing the magnitude and sign, respectively, of what will hereinafter be referred to as a "ternary analog output signal," said magnitude signal having a fixed period but a varying duty cycle.
The representation of a number may be converted from a plurality of binary coded signals to a linear analog signal using either direct digital-to-analog conversion (DAC) or indirect DAC techniques. Direct DAC, which is the more common, employs a fixed reference voltage, and provides an output voltage that is a portion of said reference voltage and has a linear relationship with the number represented by changeable, binary coded inputs. Indirect DAC employs a binary signal with a fixed period, and provides a ternary analog output signal of said fixed period whose duty cycle (i.e., fraction of the period that said output signal is not zero) has a linear relationship with the number represented by changeable, binary coded inputs. Generally, an analog device that receives the indirect DAC output is not capable of responding to changes of the ternary analog signal within the period of the signal. Rather, it responds to the average of the signal over many periods (i.e., the average of the duty cycles over said periods).